Field of the Invention
The present invention generally relates to computer science and, more specifically, to migration of peer-mapped memory pages.
Description of the Related Art
A typical computer system usually includes a central processing unit (CPU) and some sort of parallel processing unit (PPU). Some PPUs are capable of very high performance using a relatively large number of small, parallel execution threads on dedicated programmable hardware processing units. The specialized design of such PPUs usually allows these PPUs to perform certain tasks, such as rendering 3-D scenes, much faster than a CPU. However, the specialized design of these PPUs also limits the types of tasks that the PPU can perform. By contrast, the CPU is typically a more general-purpose processing unit and therefore can perform most tasks. Consequently, the CPU usually executes the overall structure of a software application and then configures the PPU to implement tasks that are amenable to parallel processing.
As software applications execute on the computer system, the CPU and the PPU perform memory operations to store and retrieve data in physical memory locations. Some advanced computer systems implement a unified virtual memory architecture (UVM) common to both the CPU and the PPU. Among other things, the architecture enables the CPU and the PPU to access a physical memory location using a common (e.g., the same) virtual memory address, regardless of whether the physical memory location is within system memory or memory local to the PPU (PPU memory).
Further, some computer architectures include multiple PPUs, for increased processing performance. In such architectures, each PPU may be associated with a local memory that stores memory pages, and with a local page table that keeps track of the memory pages stored in the associated local memory.
One drawback to including multiple PPUs in a computer architecture that implements unified virtual memory, where each PPU has a local memory and local page table is that migrating the different memory pages among the different PPU local memories becomes more complicated. For example, one difficulty that may arise is determining how to update the page table entries associated with the different memory pages when migrating memory pages among the different local PPU memories.
As the foregoing illustrates, what is needed in the art is a more effective approach to migrating memory pages in unified virtual memory architecture that implements multiple PPUs.